1. Field of the Invention
The present invention relates to a cell switch to be used in an ATM communication network system.
2. Description of the Background Art
Conventionally, a so called STM (Synchronous Transfer Mode) in which a data transfer capacity required by a communication is allocated at a time of a call set up has been used extensively for a telephone network. More recently, in order to realize the higher speed and wider bandwidth network, a so called ATM (Asynchronous Transfer Mode) in which each terminal uses a data transfer capacity of the network as much as necessary when the need for the communication arises has been developed.
In this ATM, the data are transferred in units of packets of a fixed length called cells, in which a routing information is indicated in a header of each cell. The ATM is characterized in that each terminal transfers the cells to the network according to the need for the communication such that each terminal uses a data transfer capacity of the network only as much as necessary for the communication when the need for the communication arises.
In the communication network system using the ATM, it is necessary to provide a number of cell switches which switch, i.e., distribute, the cells entering from a plurality of input transmission paths into the appropriate one of a plurality of output transmission paths according to the routing information indicated in the header of each cell.
An exemplary configuration of a conventional cell switch is shown in FIG. 1.
This conventional cell switch 101 of FIG. 1 comprises: a plurality of input transmission paths 102 including S channels #0, #1, . . . , #m from which the cells are entered; an input conversion unit 105 including a serial to parallel converter (not shown) and a multiplexer (not shown) for appropriately converting the cells entered from the input transmission paths 102; a buffer memory 107 for storing the entered cells converted by the input conversion unit 10S; a plurality of output transmission paths 112 including channels #0, #1, . . . , #m from which the cells are outputted; an output conversion unit 115 including a parallel to serial converter (not shown) and a de-multiplexer (not shown) for appropriately converting the cells to be outputted from the output transmission paths 112; and a buffer control circuit 117 for controlling the writing and reading of the cells to and from the buffer memory 107.
In this conventional cell switch 101, when the cell to be transferred through a specific channel is present in the buffer memory 107, that cell is read out from the buffer memory 107 under the control by the buffer control circuit 117, appropriately converted by the de-multiplexing and the parallel to serial conversion at the output conversion unit 115, and outputted from the specific channel of the output transmission paths 112. In a case, where is no cell in the buffer memory 107 which is to be outputted through the specific channel of the output transmission paths 112, an empty cell of a prescribed format which carries no data is automatically set for that specific channel such that the empty cell which has been appropriately converted by the de-multiplexing and the parallel to serial conversion at the output conversion unit 115 is outputted from that specific channel of the output transmission paths 112.
Now, in the ATM communication network, a plurality of such cell switches are inter-connected together in a number of steps to form a cell switch network to be able to handle a large number of input transmission paths and output transmission paths.
An exemplary configuration of a cell switch network using a plurality of conventional cell switches similar to the cell switch of FIG. 1 is shown in FIG. 2.
This cell switch network 140 of FIG. 2 comprises: a plurality of first step cell switches 141a, 141b, . . . , 141n having a plurality of input transmission paths 102a, 102b, . . . , 102n through which the cells are entered into the cell switch network 140; a plurality of second step cell switches 143a, 143b, . . . , 143n having the input transmission paths inter-connected with the output transmission paths of the first step cell switches 141a, 14lb, . . . , 141n; and a plurality of third step cell switches 145a, 145b, . . . , 145n having the input transmission paths inter-connected with the output transmission paths of the second step cell switches 143a, 143b, . . . , 143n, and a plurality of output transmission paths 112a, 112b, . . . , 112n through which the cells are outputted from the cell switch network 140, where each of the input transmission paths and output transmission paths includes the channels #0 to #m.
In this cell switch network 140, the cells in a format shown in FIG. 3 is used. Namely, each cell to be entered into this cell switch network 140 has a top bit field 31 for indicating whether this cell is a valid cell or an empty cell; a first header field 33 for indicating the routing information to be used at the first step cell switches; a second header field 35 for indicating the routing information to be used at the second step cell switches; a third header field 37 for indicating the routing information to be used at the third step cell switches; and a cell data field 39.
In the top bit field 31, a value 1 indicates that it is a valid cell while a value 0 indicates that it is an empty cell, for example. In the first, second, and third header fields 33, 35, and 37, the value indicates the channel through which it should be transmitted at the respective step. Accordingly, when this cell of FIG. 3 is entered into the cell switch network 140, the first step cell switch which received this cell will transmit it to the second step cell switches through the channel #3 according to the first header field 33, the second step cell switch which received this cell will transmit it to the third step cell switches through the channel #2 according to the second header field 35, and the third step cell switch which received this cell will outputs through the channel #5 of its output transmission paths.
Now, such a conventional multi-step cell switch network has been associated with the following problems.
First, in such a conventional multi-step cell switch network, a number of connection lines connecting the cell switches are quite numerous and each cell switch must be connected with quite a large number of other cell switches, so that it has been difficult to carry out the verification of the proper connections by the connecting lines, which is necessary at a time of installment of the device incorporating such a cell switch network for instance.
Namely, such a verification has been carried out by externally supplying a huge number of test cells designed to pass through all the possible routes inside the cell switch network from the input transmission paths of the cell switch network and by inspecting the cells outputted from the output transmission paths of the cell switch network, which is an extremely tedious and time consuming procedure.
Moreover, in such a conventional multi-step cell switch network, a number of input transmission paths and a number of output transmission paths are connected with respect to a plurality of other cell switches or external devices, so that it has been difficult to carry out the check of the cell input and output operation timings between the inter-connected cell switches or external devices.
In addition, for the similar reasons as described above, it has also been difficult in such a conventional multi-step cell switch network to carry out the check and the adjustment of the cell input and output phase relationships, i.e., the phase relationships between the system clock signals supplied to the cell switches or the external devices with respect to the timings for the input and output of the cells.
In particular, there is no way of inputting and outputting the cells directly to and from the cell switches belonging to intermediate steps in a multi-step network configuration such as the second step cell switches 143a to 143n in the cell switch network 140 of FIG. 2, so that the check of the cell input and output operation timings and the adjustment of the cell input and output phase relationships have been impossible for such cell switches belonging to intermediate steps in a multi-step network configuration.
Furthermore, the operation characteristics of the cell switch, such as an operation speed, can be affected by the temperature of the cell switch itself, so that even when the adjustment of the cell input and output phase relationships between the cell switches and the external devices are made at some point, the cell input and output phase relationships can be changed as a result of the change of the temperature of the cell switches. As a result, it has been almost impossible in a conventional multi-step cell switch network to maintain the properly adjusted cell input and output phase relationships between the cell switches and the external devices.